Our IP packages can be quickly integrated and flexibly delivered for use in custom silicon (ASIC), programmable hardware (FPGA) or as a pure software solution. A suite of reference kits and full design support is provided to reduce integration time and cost.
This highly configurable portfolio can also be tailored to optimise performance depending on communication service requirements.
The AccelerComm™ channel coding architecture is designed specifically for 3GPP 5G applications, and fully exploits the flexibility and performance opportunities inherent in the specification. The design consumes up to 40% less area and up to 50% less power per bit than competing solutions. Channel coding/decoding constitutes a significant processing overhead within the 5G physical layer and so these savings have a profound impact on overall system resources and power consumption.